From Petascale to Exascale Supercomputing Systems
Chief Engineer Data Centric Systems
I will briefly explain what Petascale and Exascale Supercomputers are, what people do with them and some of the attributes that makes these systems unique. I will then discuss the myriad of engineering considerations that went into the current generation of IBM Supercomputers. The focus will be on hardware, with topics ranging from power and cooling, network, I/O, and memory, to control, safety, resilience and service. Finally I will talk about the next generation of machines, and what may follow after that.
Evolution of Reliability Research in Microelectronics:
Jasmeet Chawla, Intel
Electrical resistance of sub 15nm metal interconnect wires
The electrical line resistance of metal interconnect increases with decreasing critical dimensions. In this work, we report electrical resistance measured data and modelling for sub 15 nm wires. We demonstrate the increase in resistance is primarily due to increase in % geometrical space occupied by less-conducting liners and due to increase in electron scattering at external surfaces. The contribution of electron-phonon scattering and grain size is smaller for narrow wires.
The talk concludes to motivate the scientific community to invent liner-less metal fill and integration schemes (eg non-Cu, subtractive patterning) or scaled liner with specular electron scattering at metal-liner interface.
Robert Fox, GLOBALFOUNDRIES
Process Window Challenges in Advanced Manufacturing-
New Materials and Integration Options
With the continued progression of Moore’s law into the sub-14nm technology nodes, interconnect RC and power dissipation scaling play an increasingly important role in overall product performance. As critical dimensions in the mainstream Cu/ULK interconnect system shrink below 30nm, corresponding increases in relative process variation and decreases in overall process window mandate increasingly complex integrated solutions. Traditional metallization processes, e.g. PVD barrier and seed layers, no longer scale for all layout configurations as they reach physical and geometric limitations. Interactions between design, OPC, and patterning also play more and more critical roles with respect to reliability and yield in volume manufacturing; stated simply, scaling is no longer “business as usual”. Restricted design layouts, prescriptive design rules, novel materials, and holistic integration solutions each therefore become necessary to maximize available process windows, thus enabling new generations of cost-competitive products in the marketplace.
C.K. Hu, IBM
Electromigration in Al and Cu alloys thin film lines: Effect of impurity and kinetics of damage formation
The electromigration characteristics and kinetics of damage formation for Al(Cu) and Cu(Mn) alloys have been investigated.1-3 The mass transport was measured as a function of temperature using drift‐velocity and resistance techniques. The flux divergence at the line/via interface was found to be responsible for formation of open and/or short failures in the interconnect structure. Progressive void growth at the cathode end was found to be responsible for open or high resistance increase failure of the line/via structures. The dominant mass transport paths in Al or Cu on‐chip interconnect are along the interfaces and/or grain boundaries. The solute Cu in Al line or Mn in Cu line at interfaces and grain boundaries drastically reduces the Al or Cu mass flow, respectively. The observed mass transport in Al(Cu) or Cu(Mn) lines can be separated into three stages: incubation, slow atom migration, and steady‐state. The depletion of materials at the via contact is preceded by an incubation period during which solute is swept out a threshold distance from the cathode of the line.The incubation period is the time necessary to sweep out solute beyond a critical length from the cathode end. The slow migration stage is the period when the depletion zone of solute at the cathode end slightly exceeds the critical length at which the stress‐induced flow can no longer compensate the electromigration flux. As the test continues, the solute depletion zone at the cathode end increases beyond the critical length and a final steady‐state similar to electromigration in pure metal lines is reached. Using the proposed model, the electromigration mean lifetime is related to current density, j-n, where m is between 2 to 1.
Fabrice Nemouchi, CEA LETI
Source and Drain Contact Challenges for 14 and sub-14 nm FDSOI CMOS
The microelectronics industry and CMOS devices in particular, encountered drastic challenges on the down scale route in order to fulfil the demand such as low voltage, low power, high performance and increased functionalities. Thus, continuous modifications of BEOL and FEOL have been implemented during the two past decades while the typical pitch size of the device dropped below 100 nm. Moreover, those evolutions lead to two new paradigms based on the FinFet and FD-SOI architectures. In both cases, the contact brick, which embedded the extensions, the junctions, and source & drain (S&D) contact, is part of the main roadblocks from generation to generation development. Because of the design but also due to the global performance estimations, a clear discrepancy in contact strategy has been adopted. While on FinFet the contact is elaborated into trenches, the planar FD-SOI architecture kept the silicide process using Ni-based solid state reaction with high doped raised S&D. In this work, we review the CMOS brick contact evolution from bulk to FD-SOI. We especially focus on the constraints that silicide formation had to face, the current concerns and the coming challenges for alternatives contact.
Anthony J. Annunziata
IBM T. J. Watson Research Center
BEOL Metallization Challenges for MRAM
New memory technologies such as magnetoresistive random-access memory (MRAM), phase change memory (PCM), and various resistive random access memories (RRAM) are being developed by many companies, with the first products now in or close to production. One commonality among most of these memories is that they involve many new BEOL integration challenges. I will focus on two varieties of MRAM as exemplars of these challenges. In particular, I will discuss the research and development of thermally-assisted MRAM (TAS-MRAM) and spin transfer torque MRAM (STT-MRAM) at IBM. I will start with an introduction to how these memories operate and describe the basic device physics that underpins them. I will then focus on the challenges and requirements that they pose, in particular with integration of new magnetic materials, new patterning and encapsulation processes, and novel contact schemes into the BEOL. I will discuss structural and device degradation challenges to yield, and explain the key aspects of successfully integrating Mb-scale arrays of MRAM devices into demonstrator chips in 90 nm CMOS, focusing on the development of a low temperature, low degradation, and low stress BEOL. I will conclude with outlining the challenges that lay ahead in successfully integrating MRAM with advanced nodes (32 nm and beyond).
Microelectronics Research Center, UT-Austin
Contact Engineering for Novel Transistors in 2D Materials
Two-dimensional materials such as graphene and transition metal dichalcogenides have opened up avenues in beyond-Si CMOS device concepts involving high frequency, flexible electronics. They can also lead to novel, ultra-low power transistors based on single or many-particle 2D-2D tunneling. However, there are many process challenges that need to be resolved, including low resistance ohmic contacts to these materials. We will discuss recent advances in contact engineering.
Steven Mayer, Lam Research
Principles and Advances in 2.5 and 3D-IC Packaging Electrodeposition
Over the course of the electronics industries growth, electroplating operations have grown steadily because of the incessant market forces of improved device performance and manufacturing cost reductions. Examples include the adaptation of circuit board plating (displacing screen printing), solder metallization (replacing dipping and ball placement) and C4 “flip chip” interconnect bonding. The same combination of relentless manufacturing cost and performance drivers propelled copper-dual-damascene bottom-up electroplating to displace aluminum front-end metallization around the turn of the century. Today, many serial mechanical packaging operations (e.g. ball placement, screen printing, and wire bonding) are falling victim to the same progressive cost and performance pressure historical-trends. Electrodeposition, a wafer scale parallel-processing advanced metallization technique, can be used to create thin packages and ultra-fine, high I/O structures at minimal cost. Package-related bandwidth limitation and thin, light-weight and energy efficient mobile market specific requirement are driving an exploding demand for more advanced electrochemical packaging manufacturing. This is the underlying reason for electroplating’s rapidly expanding adaptation in the post-passivation packaging arena.
The general goal of wafer-level-packaging electrodeposition is to achieve a highly uniform film deposition on all structure sizes/scales across a wafer. The die and feature size/scale, pattern layout, and metallization-bath-chemistries physical properties interact with the process (current, flow rate, temperatures) and reactors design to influence the resultant thickness distribution via their impact on electric- and convective-field-distribution. To simplify the complex multi-parametric metallization problem, I’ll discuss key electrochemical-engineering principles and dimensionless-scaling-relationships, and apply these to the field of 3D-IC packaging. This knowledge is useful to a) anticipate the wafer, die and feature scale non-uniformity behavior trends, b) propose uniformity and yield enhancing alternatives, c) efficiently screen plating baths chemistries and optimize the constituent formulation, d) understand the process parameters and reactor designs impact on product quality, and ultimately e) improved overall manufacturing yield and reduce costs. Finally, I’ll discuss the theory-of-operation for our recently-introduced wafer-level-packaging electrodeposition reactor series, and our missing-die azimuthal non-uniformity compensation processes (such as seen with die-reconstituted wafers).
Prof. Jim Leu
National Chiao Tung University
Low-k SiCxNy Etch-stop/Diffusion Barrier Films for Back-end Interconnect Applications
Lower k and low leakage silicon carbonitride (SiCxNy) films were fabricated using single precursor under low plasma power density using radio-frequency (RF) plasma-enhanced chemical vapor deposition (PECVD). We explored precursors with (1) cyclic carbon containing structures, (2) higher C/Si ratio, (3) multiple vinyl groups, as well as (4) the incorporation of porogen for developing low-k SiCxNy films as etch-stop/diffusion barrier (ES/DB) layer for copper interconnects in this study. SiCxNy films with k values between 3.0 and 3.5 were fabricated at T≦ 200 oC, and k~4.0-4.5 at 300-400 oC. Precursors with vinyl groups yielded SiCxNy films with low leakage, excellent optical transmittance and high mechanical strength due to the formation of cross-linked Si-(CH2) n-Si linkages.
Prof. Zhihong Chen, Purdue University
Improved Electrical and Thermal Performance and Ultra-thin Diffusion Barrier in Copper-Graphene Hybrid Interconnects
Copper-graphene hybrid interconnects (Cu-G) were fabricated through direct growth of graphene on thin Cu wires using a CMOS-compatible process, demonstrating enhanced electrical and thermal properties. We successfully coated 180 nm-wide and 60 nm-thick Cu wires with graphene using a novel plasma process. Cu-G wires show 10-15% lower resistivity compared to the “Cu with no graphene” (Cu-NG) wires. Lower Joule heating was observed at high current densities in the hybrid interconnects, especially for longer wires. Moreover, graphene acts as an effective diffusion barrier between Cu and inter-layer dielectric (ILD) after extensive thermal stress, meeting the ITRS target of a 1-1.5 nm thick diffusion barrier for the year 2017.