Tom Andre, Everspin
Spin-Torque MRAM Fundamentals
Magnetoresistive Random Access Memory (MRAM) technology was introduced into the market last decade in the form of Toggle MRAM, available in densities up to 16Mb. In the last few years, Spin-Torque MRAM, the next generation of Magnetic Tunnel Junction (MTJ) based memory, has become available offering higher density and bandwidth with 64Mb and 256Mb DDR3 products introduced by Everspin and a 1Gb DDR4 product in development. ST-MRAM enables a wide range of applications as both stand alone component memory and embedded memory. One key advantage MTJ based memory offers as embedded memory is the ability to integrate the MTJ memory element in the metal stack, which decouples the integration from the CMOS technology node and accelerates the introduction of non-volatile memory into advanced process nodes. An overview of ST-MRAM fundamentals will be presented.
Katayun Barmak, Philips Electronics Professor/ Columbia University
Copper and Interconnects Beyond Copper
Power consumption by Cu interconnects is an issue of critical concern. While much of the work in the semiconductor community has focused on novel three wire electronic logic devices for increased energy efficiency, the more urgent need for better wires at the device level has only been addressed by incremental improvements. The increased power consumption in Cu interconnects is a consequence of the resistivity size effect, wherein conductors with dimensions near or below the mean free path of electrons exhibit higher resistivity than bulk conductors. In this talk, I will present our studies of the impact of surfaces and grain boundaries on Cu resistivity. These studies made use of crystal orientation mapping in the transmission electron microscope for vastly improved nanoscale metrology. The anisotropy of the resistivity size effect in oriented single crystal nanowires of W and the future of interconnects beyond Cu will also be discussed.
Atashi Basu, Applied Materials
Atomistic Simulations of Barrier Properties for BEOL Applications
First-principles simulations are performed to analyze the barrier properties of Ta-Nitride films for Cu diffusion. Different variant of Ta-Nitride films (PVD and ALD) are considered in this study. Interstitial diffusion mechanisms through various films are considered. Thermodynamic and kinetic results illustrate that PVD films have higher barrier for Cu diffusion compared to ALD films.
Takeshi Nogami, IBM
Cu with Through-Co Self-Forming Barrier vs. Alternative Conductors for 7 nm BEOL and Beyond
In 7nm BEOL and beyond, the scaling factor for interconnect RC is no longer k, but 2k – 3k due to increased contribution of surface / grain boundary scattering of electrons. The advanced Cu metallization process, “through-cobalt self-forming barrier” (tCoSFB) has promise to extend Cu interconnects to mitigate the abrupt increase in RC without losing electromigration (EM) / TDDB reliability, whereas alternative conductors such as Co and Ru interconnects are being studied. Line resistance (R), EM and TDDB reliability are compared and discussed among tCoSFB Cu, conventional Cu interconnects, and Co and Ru interconnects.
Chris Penny, IBM
Reliable Airgap BEOL Technology in Advanced Interconnects for
Substantial Power and Performance Benefits
In recent years, airgap technology has been implemented at fat-wire levels; however, a significant enhancement in chip performance can be gained by including airgaps in the finest wiring levels as well. This paper demonstrates the first reliable and low cost airgap BEOL technology, generated at extremely tight dimensions (48 nm pitch) in Cu/ULK. This provides 20% nested-line capacitance reduction relative to the ungapped Cu/ULK baseline. This result is of critical importance, as it validates that airgaps can be extended down to ultrafine wire levels, such as for the 7nm or 10 nm technology nodes. To achieve this, we benefitted from several elements which address various process, integration, and reliability challenges associated with airgap formation at such small dimensions. We present data and explanations of these solutions, and their impacts on yield, performance, defectivity and reliability (EM and TDDB).
Saurabh Sinha, ARM
The "interconnect problem" and potential solutions for the end-of-Moore's law scaling area
As we near the end of Moore's law scaling, the dominance of interconnect parasitics in determining system performance and power are rapidly increasing. In particular, increasing conductor resistivity due to prominent size effects at scaled dimensions can critically impact designs and extensive research is being conducted to find alternate low-resistivity materials to replace copper interconnects. This talk will focus on design-technology co-optimization (DTCO) research of interconnect material systems and their impact on product-level metrics. Additionally, the importance of system-level benchmarking to evaluate disruptive technology choices will be highlighted. This talk will present some benchmarking results evaluating novel low-resistivity materials such as graphene interconnects, extensive studies on 3D integration and efforts towards system-level interconnect modeling to tackle the 'interconnect problem'.
Marleen H. Van der Veen, Research Scientist IMEC
Extending the Cu metallization and Alternatives
Cu interconnects with barrier (Mn-based, TaN) /liner (Co, Ru) are compared for resistivity, resistance scaling, and electromigration (EM) performance. The Ru-liner Cu schemes show a higher Cu-resistivity that can be compensated by a thinner Mn-based barrier. The Jmax benchmarking shows a significant improvement for the scaled Mn-based/Ru system, making it a serious candidate to extend the Cu metallization. The extendibility beyond 16nm copper width was explored experimentally and benchmarked with Ru full fill damascene data. Beyond the 12nm half pitch, more disruptive material like Ru will be necessary while the interconnect scaling proceeds.